1. Field of the Invention
The present invention relates to methods and systems for optical proximity correction (hereinafter referred to as “OPC”) for layout design and verification processing of mask data for semiconductor integrated circuits.
2. Description of the Related Art
With the miniaturization of semiconductor integrated circuits in recent years, it has become difficult to generate precise minute mask patterns on a wafer through optical exposure. As a result, in order to generate minute mask patterns, certain graphics are added on the mask pattern in advance, or OPC is conducted which corrects the dimension of the pattern depending on the density of the pattern. OPC can be grouped into two categories: rule-based OPC and model-based OPC. The “rule-based OPC” is a method wherein a correlation table between the distortion and the proximity effect is prepared for each line width and space, based on the actual measurement obtained from the pattern transferred by an OPC test, in order to establish rules for correcting the layout patterns. The correction is conducted according to those rules. That is, the rule-based OPC is a method to generate OPC patterns based on the OPC pattern generation rules specified for each pattern category of the circuit patterns. The rule-based OPC is effective when adjacent figures are checked in one-dimension for correction, such as line and space patterns. On the other hand, the “model-based OPC” is a correction which uses lithography simulation-based models. According to the “model-based OPC”, a model is calibrated based on the actual measurement obtained from the transferred pattern in order to handle more complicated processes. That is, according to the model-based OPC method, a model equation simulating a dimension expected to be obtained after processing is used to calculate the dimension of the post-process mask pattern to make it match the dimension of the design pattern. This model-based OPC is effective when adjacent figures are checked in two-dimensions for correction. The model-based OPC takes much more processing time than the rule-based OPC, but has higher accuracy for corrections in general. The leading edge devices of recent years require two-dimensional OPC, thus, the model-based OPC, which can be realized comparatively easily, is employed. Also, an approach combining the rule-based OPC and the model-based OPC is also implemented.
However, after the process has been conducted for numerous processing generations, an increasing number of patterns cannot be corrected properly, and a more accurate OPC becomes necessary. Unfortunately, the model-based OPC fails to solve this problem in practice, because it is difficult for the model-based OPC to correct all patterns by a calibration based on actual measurements, in terms of the time necessary for the actual measurement and the enormous amount of data. In order to mitigate the above problem, the following methods are employed:
1) when there is any region which requires different accuracy, a model is specifically designed for that region and applied to the intended region accordingly, and
2) when accuracy can be improved by designing a model (rule) specifically for each process such as mask production, lithography upon the wafer, and wafer processing after the lithography such as etching (for example, the proximity effect in the etching process may be different from that in other processes), different models (rules) are designed for each process to conduct correction specific to that process.
In the conventional OPC processing, it takes a lot of time for the lithography simulation to obtain a transferred image, and it also takes a lot of time and many processes to analyze the pattern which is output as a hazardous part and to determine an appropriate corrective treatment, which prolongs the verification time. In addition, a flow in which the lithography rule check, after the OPC is conducted for each region (logic part, peripheral memory part, side of memory cell) and each process (etching process, lithography process, mask production process), and detailed simulation of the transferred image is conducted, must be repeated many times, which significantly prolongs the manufacturing time of a semiconductor integrated circuit. In addition, conventionally, each time a nonconformance pattern is discovered in a process or a region, the process must return to the very beginning of the work-flow to correct the OPC setting or the layout design, which also adds time to the overall manufacturing process. Furthermore, although efforts are made to improve accuracy by adjusting the OPC setting based on the result of the OPC verification, accuracy may be degraded by any side effects on other patterns, which makes the optimization of OPC processing difficult.
As shown in FIG. 1A, the edges to be corrected by the OPC can be grouped into a line edge 80a, a line section 80b, an inner corner 80c, and an outer corner 80d, for example. To begin with as shown in FIG. 1B, suppose a correction using a rule or a model without a restriction (or a default rule or model) is made on the part where the line edge 83a in the pattern 81 and the outer corner 84a in the pattern 82 are close. In this case, the space between the FIGS. 81 and 82 is narrowed due to the existence of the correction parts 83b and 84b as shown in FIG. 1C, which may lead to a short-circuit between the FIGS. 81 and 82 after transfer. Therefore, in the OPC processing, a restrictive value must be set to guarantee appropriate minimum space between the line edge 83c and the outer corner 84c, in order to avoid short-circuiting, as shown in FIG. 1D.
A corrective treatment specially used for each pattern type can be designed by setting detailed corrections for each type of edges 80a, 80b, 80c, and 80d in FIG. 1A. In practice, however, it is difficult to apply such specific corrective treatments flexibly to a new pattern variation. For example, as shown in FIG. 1D, a correction may need different limit values for different cases, depending on the region surrounding the pattern and differences in the line width of the patterns.
Furthermore, if optimal OPC is conducted for each section on the chip including a logic section, and a memory section (the inside of the memory cell, the edge of the memory cell, and the periphery of the memory cell) in a memory integrated chip, or for each process including the reticle production process, wafer lithography process, or etching process, the accuracy is only improved on average. Some patterns may not be corrected appropriately, so that a corrective treatment specifically designed for each pattern becomes necessary. The memory section is further divided into the inside of the memory cell, the edge of the memory cell and the periphery of the memory cell, each of which needs a different OPC.
As described, the conventional method fails to complete OPC in a short period of time, and does not conduct appropriate correction on every variation of the patterns.